1. Field of the Invention
This invention relates to modeling of logic devices which is required during logic simulation of digital designs.
2. Description of the Prior Art
Currently, either computer programs running on general-purpose computers or special-purpose computers are used to simulate the operation of digital designs. The simulation of such designs is used to test the operation of the design before the design is physically implemented as a printed circuit board or an integrated circuit. Each design is represented as a collection of interconnected logic devices. The logic simulator must evaluate the behavior of each logic device and simulate the effects of the interconnections between the devices. This invention describes a technique whereby a logic simulator can evaluate the behavior of a logic device.
For any number of reasons, there is an increasing emphasis upon the simulation of digital designs. This increase in emphasis is causing a related increase in the requirements placed upon logic simulators. There is a need for improved performance as well as improved accuracy in device modeling.
Currently, there are three classes of logic simulator: software, firmware, and hardware. Software logic simulators provide a performance of a few thousand events per second; firmware simulators, a performance of a few tens of thousand events per second; and hardware simulators, a performance of a few hundred of thousand events per second. Software simulators can typically model simple combinatorial logic elements, simple memoried logic elements, and complex memoried elements; firmware simulators can typically model simple combinatorial and memoried elements; hardware simulators can typically model only combinatorial elements.
Thus, the simulation user has a choice between speed and modeling ability. It must be noted that simple memoried elements can be constructed from combinations of combinatorial gates, and that complex memoried elements can be constructed of combinations of simple memoried elements and simple combinatorial elements. Thus, any of the classes of simulator can be used to simulate a given circuit. However, the use of multiple elements to represent a single element will result in multiple events being used to represent a single event, and thus a loss of performance. For example, whereas a software simulator might represent a JK flip-flop as a single logic element, a hardware simulator might use a combination of 9 combinatorial gates. On average, the hardware simulator will require five events to simulate the behavior of the JK flip-flop, whereas the software simulator will require only one event. Thus, the effective events per second of the hardware simulator is only 1/5th of its designed rate and consequently the hardware simulator will be only 20 times faster than the software simulator.
The need for speed is an undeniable aspect of logic simulation. A modest microprocessor built with today's technology may consist of 100,000 transistors. These 100,000 transistors can easily represent 20,000 logic elements of the sort that logic simulators process. To understand the implications of these numbers, consider the approximation that each clock cycle will produce approximately 2,000 events. Consider also the fact that it will take about 10,000,000 clock cycles to simulate just one second of operation. Thus, we can compute that to simulate one second of operation will require 20,000,000,000 events. A software simulator that processes 2,000 events per second will take 10,000,000 seconds to perform the simulation. This is a little over 155 days. A firmware simulator that processes 20,000 events per second would require 1,000,000 seconds, or 15 days. A hardware simulator that processes 200,000 events per second could finish the simulation in 27 hours.
The example of the microprocessor also highlights the value of improved device modeling. If the use of more complex device models can reduce the number of logic devices from 20,000 to 10,000, then the hardware simulator could finish the simulation overnight.